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Difference between revisions of "S5L8720 (Hardware)"
ChronicDev (talk | contribs) (→ARM7 (Second CPU)) |
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| − | This should help people reversing iBoot and friends. It is a work in progress. |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==SHA1== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center><b>Base</b>: 0x38000000</center></td> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x00</center></td> |
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| − | <td width=50%><center>Configuration</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x04</center></td> |
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| − | <td width=50%><center>Setup</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x20 through 0x30</center></td> |
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| − | <td width=50%><center>Output SHA1 hash</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x40 through 0x7C</center></td> |
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| − | <td width=50%><center>Data Input (64 Bytes)</center></td> |
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| − | </tr> |
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| − | </table> |
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| − | See [[S5L8720 (Hardware) SHA1|S5L8720 SHA1]] for a more detailed description |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==DMA (PL080)== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | This appears to use an ARM PrimeCell PL080. You can read the technical reference manual [http://www.mediafire.com/download.php?mjy2m1do0jg here]. |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center><b>Base (dmac0)</b>: 0x38200000<br><b>Base (dmac1)</b>: 0x39900000</center></td> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | </tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x0</center></td> |
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| − | <td width=50%><center>Interrupt Status</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x4</center></td> |
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| − | <td width=50%><center>TC Status (If HIGH, transaction complete)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x8</center></td> |
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| − | <td width=50%><center>TC Interrupt Clear</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0xC</center></td> |
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| − | <td width=50%><center>Error Interrupt Status</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x10</center></td> |
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| − | <td width=50%><center>Error Interrupt Clear</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x14</center></td> |
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| − | <td width=50%><center>TC Interrupt Status Before Masking (Raw)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x18</center></td> |
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| − | <td width=50%><center>Error Interrupt Status Before Masking (Raw)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x1C</center></td> |
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| − | <td width=50%><center>DMA Channels Enabled</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x30</center></td> |
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| − | <td width=50%><center>Controller Configuration</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x34</center></td> |
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| − | <td width=50%><center>Enable / Disable Synchronization</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x100</center></td> |
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| − | <td width=50%><center>Channel 0 Source Address</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x104</center></td> |
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| − | <td width=50%><center>Channel 0 Destination Address</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x108</center></td> |
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| − | <td width=50%><center>Channel 0 Linked List Address</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x10C</center></td> |
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| − | <td width=50%><center>Channel 0 Control 1</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x110</center></td> |
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| − | <td width=50%><center>Channel 0 Control 2</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x114</center></td> |
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| − | <td width=50%><center>Channel 0 Configuration</center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==VIC (PL192)== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | This appears to use an ARM PrimeCell PL192. You can read the technical reference manual [http://www.mediafire.com/download.php?mmjdnud0iuz here]. |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <b>Base (vic0)</b>: 0x38E00000<br> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <b>Base (vic1)</b>: 0x38E01000</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x0</center></td> |
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| − | <td width=50%><center>IRQ Status</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x4</center></td> |
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| − | <td width=50%><center>FIQ Status</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x8</center></td> |
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| − | <td width=50%><center>Raw Interrupt Status</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0xC</center></td> |
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| − | <td width=50%><center>Interrupt Select (0=IRQ, 1=FIQ)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x10</center></td> |
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| − | <td width=50%><center>Interrupt Enable (0=Disabled, 1=Enabled)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x14</center></td> |
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| − | <td width=50%><center>Interrupt Enable Clear (Write-Only; 0=No Effect, 1=Interrupt enabled with previous reg disabled)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x18</center></td> |
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| − | <td width=50%><center>Software Interrupt (0=Disabled, 1=Enabled)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x1C</center></td> |
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| − | <td width=50%><center>Software Interrupt Clear (Write-Only; 0=No Effect, 1=Interrupt enabled with previous reg disabled)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x20</center></td> |
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| − | <td width=50%><center>Register Protection Mode. If bit 0 is set to 1, then Protection Mode is on and only privileged mode writes will work.</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x24</center></td> |
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| − | <td width=50%><center>Software Interrupt Priority Mask (0=Masked, 1=Not Masked)</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x100</center></td> |
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| − | <td width=50%><center>Vector Addresses</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x200</center></td> |
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| − | <td width=50%><center>Vector Priority Levels</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0xFE0 through 0xFEC</center></td> |
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| − | <td width=50%><center>Peripheral Identification Registers<br><br> |
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| − | <b>Part Number</b><br> |
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| − | Bits 7 through 0 of register 0xFE0 is one portion of the part number (0x92), then bits 3 through 0 of register 0xFE4 is the other portion of it (0x1). If you do some annoying shifting, to put it together, you get 0x192 (0x92|0x11<<8&0xFFF==0x192). 0x192 indicates that it is an ARM PrimeCell PL192.<br> |
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| − | <b>Designer</b><br> |
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| − | Bits 7 through 4 of register 0xFE4 is one portion of the designer tag (0x1), then bits 3 through 0 of register 0xFE8 is the other portion of it (0x4). Like above, we can do (0x11 | 0x4<<4) and we get 0x41, which is "A" in ASCII, meaning it was designed by ARM Limited.<br> |
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| − | <b>Revision Number</b><br> |
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| − | Unlike the above two, this one is pretty easy. Bits 7 through 4 of register 0xFE8 is the revision number, which is "0" at least for the iPod touch 2G.<br> |
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| − | <b>Configuration</b><br> |
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| − | The reference manual simply states that bits 7 through 2 should read back as 0, and nothing more about them. It also states that bits 1 through 0 indicate the number of interrupts supported, which appear to be 32 for the iPod touch 2G ('''0b00=32 Supported''', 0b01=64 Supported, 0b10=128 Supported, 0b11=256 Supported).<br> |
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| − | </center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0xFF0 through 0xFFC</center></td> |
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| − | <td width=50%><center>PrimeCell Identification Registers<br><br> |
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| − | <b>Register 0xFF0</b>: Should read as 0x0D<br> |
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| − | <b>Register 0xFF4</b>: Should read as 0xF0<br> |
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| − | <b>Register 0xFF8</b>: Should read as 0x05<br> |
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| − | <b>Register 0xFFC</b>: Should read as 0xB1</center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==CHIPID== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | All information here was gathered by reversing iBoot and friends. |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center><b>Base</b>: 0x3D100000</center></td> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | </tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x0</center></td> |
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| − | <td width=50%><center>Unused & Unreferenced Register</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x4</center></td> |
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| − | <td width=50%><center>Not yet documented</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x8</center></td> |
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| − | <td width=50%><center>Chip Info<br><br> |
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| − | <b>Chip ID</b>: Bits 31 through 16 (0x8720, meaning it is an [[S5L8720]])<br> |
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| − | <b>Security Epoch</b>: Bits 15 through 1 (0x01)<br> |
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| − | </center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==WDT (Watchdog Timer)== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center><b>Base</b>: 0x3C800000</center></td> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x0</center></td> |
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| − | <td width=50%><center>Control Register<br><br> |
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| − | <b>NOTE: It seems that you can disable Watchdog Timer by rewriting this register to 0x00000000, and you can reboot the device by rewriting it to 0x100000</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x4</center></td> |
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| − | <td width=50%><center>Watchdog Timeout Duration</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0xC</center></td> |
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| − | <td width=50%><center>Interrupt Clear</center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==Timers== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | See separate article [[S5L8720 Timers (Hardware)]] |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==ARM7 (Second CPU)== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | All information here was gathered by looking at the code for the [[ARM7 Go]] command, as well as noting that although 2.1.1 iBoots reference this as 0xB8600000, 0x80000000 through 0xFFFFFFFF is mapped to 0x0 through 0x7FFFFFFF when the MMU does it's stuff. |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center><b>Base</b>: 0x38600000</center></td> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | </tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x100</center></td> |
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| − | <td width=50%><center>Running Status<br><br> |
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| − | <b>To halt the ARM7</b>: Clear all bits then set bit t 2<br> |
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| − | <b>To make it resume</b>: Set bit 1</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x110</center></td> |
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| − | <td width=50%><center>Code Address<br><br> |
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| − | To run code, halt the ARM7, write the load address of the code to this register, write 0x3FF0000 to register 0x114, then resume the ARM7</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center>0x114</center></td> |
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| − | <td width=50%><center>"Code Waiting"<br><br> |
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| − | I don't know exactly what this register does, but I named it like this because 0x3FF0000 is written to this register when there is a load address of code to be jumped to in register 0x110</center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==UART== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <b>Base (uart0 - Serial)</b>: 0x3CC00000<br> |
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| − | <b>Base (uart1 - Bluetooth)</b>: 0x3DB00000<br> |
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| − | <b>Base (uart2)</b>: 0x3DC00000<br> |
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| − | <b>Base (uart3)</b>: 0x3DD00000<br></center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==SPI== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <table border=1 width=100%> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <tr> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <td colspan=2><center> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | <b>Base (spi0 - NOR Flash)</b>: 0x3C300000<br> |
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| − | <b>Base (spi1 - NOR Flash)</b>: 0x3CE00000<br> |
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| − | <b>Base (spi2)</b>: 0x3D200000<br> |
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| − | <b>Base (spi3)</b>: 0x3DA00000<br> |
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| − | <b>Base (spi4 - Multi Touch)</b>: 0x3E100000</center></td> |
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| − | </tr> |
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| − | <tr> |
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| − | <td width=50%><center><b>Register</b></center></td> |
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| − | <td width=50%><center><b>Description</b></center></td> |
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| − | </tr> |
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| − | </table> |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | ==Links== |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | * [http://github.com/planetbeing/iphonelinux/tree/27b57ac836053d59421a02755920b5be6b1e7805/openiboot OpeniBoot] |
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| + | Haxed by 1337Urmom at The Pois0nhack team |
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| − | * [http://code.google.com/p/chronicdev/wiki/N72APDevTree Decoded iPod touch 2G DevTree] |
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Revision as of 06:21, 7 November 2009
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